1. Technical Field
The present invention relates to a semiconductor device, a physical quantity sensor, an electronic apparatus, and a moving object.
2. Related Art
Currently, physical quantity sensors capable of detecting various physical quantities, such as an acceleration sensor that detects acceleration and a gyro sensor that detects angular velocity, are broadly used in various systems and electronic apparatuses. In recent years, very high reliability is required of various physical quantity sensors as these physical sensors are installed on automobiles. To secure high reliability, it is necessary to detect a failure (defect) of a semiconductor device (IC) that processes an output signal from a sensor element, with a probability of almost 100% in the inspection process. As a technique for efficiently detecting a wiring failure (defect) in a digital circuit included in the semiconductor circuit (IC), a scan test is widely known in which flip-flops included in the digital circuit are scanned, a test pattern generated by an ATPG (auto test pattern generation) tool is serially inputted to the scanned flip-flops (scan chain), then the scan chain is canceled so that the digital circuit operates normally, the scan chain is configured again and a signal taken into the flip-flops in normal operation is serially outputted outside, and the signal is compared with an expected value to determine whether there is a failure or not. In a scan test, a failure detection rate of approximately 90% is easily achieved. However, a certain measure needs to be taken in order to achieve a failure detection rate closer to 100%. For example, the failure detection rate can be made closer to 100% by inserting observation flip-flops into all the nodes where a logical change cannot be detected despite its presence. However, this technique leads to a significant increase in circuit scale due to the insertion of a large number of flip-flops.
Meanwhile, JP-A-11-271401 proposes a technique in which, when a scan test is carried out, the logic state in another combinational circuit is taken into a flip-flop for forming a shift register in a sequential circuit to be a test target. According to this technique, a flip-flop for forming a shift register is used as an observation flip-flop at the time of the scan test, without adding a new flip-flop. Therefore, the failure detection rate can be improved while an increase in circuit scale can be restrained.
However, the technique disclosed in JP-A-11-271401 lacks versatility because a flip-flop used as an observation flip-flop is limited to a flip-flop forming a shift register. Moreover, in the technique of JP-A-11-271401, in addition to a scan selection signal that causes a flip-flop to operate as a scan circuit shift register, a scan mode signal for supplementary observation operation in order to take in the logic state in a combinational circuit to be observed in the test needs to be additionally provided, and the selection logic of the input signal and the control signal of the selector need to be changed between the flip-flop forming the shift register and the other flip-flops. Therefore, the scan test design becomes complicated, leading to design errors.